WLP Workshop 2016
Room 205, Electronics & Information Engineering Building (2F), Global Campus, Kyung Hee University, Suwon, Korea.   /   2016년 10월 06일
 
행사가 개최되었습니다.

세부프로그램

Time Topic Chair/Speaker
09:00-09:20 Registeration  
09:20-09:30 Opening Young-Hyun Jun, President
(The Semiconductor Society, IEIE)
Session-1 : Trends and Market
Session Chair :
Dr. Seung Wook Yoon (Statschippac)
09:30-10:10 Trends in Wafer Level Packaging Santosh Kumar
(Director of 3D-IC, Yole)
10:10-10:50 Wafer Level Packaging, Driving 3D Hetergeneous System Integration  From 3D-System-in-Package to 3D-System-on-Chip Soon-Wook Kim
(IMEC)
10:50-11:10 Coffee Break
11:10-11:50 Fanout Packaging Technology as Device Integration Solution Jong-Heon Kim
(VP of Development, Nepes)
11:50-12:30 High Density Fanout Wafer Level Technology Jin Young Khim
(VP of R&D, Amkor Technology)
12:30-14:00 Lunch & Social
Session-2 : Technology Development
Session Chair :
Dr. Tae-Je Cho (Samsung Semiconductor)
14:00-14:30 Market Demand and Lithography Solutions Alex Chow
(VP of Product Marketing, Ultra Tech)
14:30-15:00 Thinning and Singulation Technology for Advanced Packaging Youngsuk Kim
(DISCO)
15:00-15:20 Coffee Break
15:20-15:50 Development of Novel Low-Temperature Curable Positive-Tone Photosensitive Dielectric Materials with High Elongation Ryoji Okuda
(Principal Engineer of R&D, Toray)
15:50-16:20 Trends in Encapstulation Materials for WLP Takeshi Mori
(Head of R&D, Sumitomo Bakelite)
16:20-17:00 Wafer Level Packaging Development Seung Wook Yoon
(Director of Product and Technology Marketing, Statschippac)
17:00-17:10 Closing Prof. Joong-Whee Cho, V.President
(The Semiconductor Society, IEIE)

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