WLP Workshop 2016

초대의 글

Invitation

This year, the workshop focuses on FO-WLP (Fan-out Wafer Level Package).

FO-WLP (Fan-out Wafer Level Package) is getting significant momentum as a small form-factor solution. The application of FO-WLP is expanding rapidly, ranging from small devices to high-end mobile processors and SiP modules.

High yielding integration of FO-WLP is requiring innovative breakthroughs in all areas including IC chip finish, RDL fabrication processes, measurement and inspection technology, and verifications tools. Equipment and materials are key elements to be innovated.

Close collaboration among industry, universities, and research institutes is crucial to resolve those challenges. The organizers of the workshop have invited leading experts from diverse sites to share their expertise and experiences with others who need guidance and advice.
You are cordially invited to the forum of informative lecture and open discussion with leaders in FO-WLP technology.

Young-Hyun Jun (President, Semiconductor Society, IEIE)
Joonghwee Cho (Vice President, Semiconductor Society, IEIE)
Jinsang Kim (Workshop Organizer)
Tae-Je Cho (Workshop Organizer)